The invention relates to an integrated electronic device comprising a mechanical stress protection structure.
As is known, the techniques of advanced photolithography (such as ultraviolet electromagnetic radiation, X rays) allow integration of millions of transistors and electronic components of circuits on the scale of ULSI in areas of silicon of several square millimeters. This very high integration level enables the circuit functionalities of the devices to be increased but also involves an increase in the number of pins and corresponding contact pads required for connection of the integrated device to the system which cooperates therewith, such as extremely fast microprocessors with a large number of bits.
Because of the increase in the pad number and the corresponding reduction of the device minimum dimensions, the space required for the interconnections becomes an increasingly large fraction of the area of the chip. To avoid this problem, the actual dimensions of the bonding pads and the space between them would have to reduce; there are, however, limiting factors (minimum dimensions of the bonding wire; alignment mechanical tolerances of the wires on the pads) which cause the minimum dimension areas of the pads to be of some tens of microns. These dimensions, on the other hand, are particularly large if compared to the minimum lithographic dimensions, of the order of tenths of a micron.
Consequently, in case of integrated devices with a large number of pads, the area intended for the interconnections represents a high percentage of the chip total area and furthermore, sometimes, the total dimensions of the chip become unacceptable; in this situation it would be appropriate to integrate part of the electronic devices in the zones underneath the pads. This is rarely possible, however, in that the mechanical deformations induced in the area of the pads during the wire bonding phase expose the devices underneath to not insignificant problems of reliability.
In particular, during wire bonding, mechanical stresses may occur on the metal/dielectric interfaces because of the different Young and rigidity moduli of the materials and these stresses may cause delaminations and/or fractures of the different layers and/or mechanical compression states. These phenomena may give rise to anomalies in the correct operation of the device. For example, delaminations and/or fractures may cause problems of current leakage, induced surface contamination, changes of parasitic thresholds; the state of stress may locally alter the crystallographic orientation of the single-crystal lattice of the silicon, inducing variations in the electrical parameters of the components (variations in density of surface layers and hence a change in the natural threshold of MOS devices and of the beta parameter of bipolar transistors, etc.).
Integration underneath the pad would be desirable, for example, in case of integration of electrostatic discharge protection circuits which act only during chip handling and are also of considerable size compared with the other circuits, thus occupying a not insignificant area of silicon which could otherwise be used for various circuit functions. Furthermore, integration underneath the pads also appears advantageous for extremely fast devices in which the parasitic resistances and capacitances associated with the interconnections limit the maximum use speed of the device; in this case, therefore, it is desirable to reduce the interconnection length as much as possible, as is possible in case of components integrated directly underneath the respective pads, so that the parasitic components can be minimized and the integrated device speed performance consequently optimized.
An object of the invention is therefore to provide a protection structure which enables active devices to be integrated underneath the pads.
According to one aspect of the present invention, an integrated electronic device is provided, as defined, for example, in claim 1.